To calculate Fcy, we need to determine the division factor used by the PLL. Let's assume the division factor is N.
The PLL input clock frequency (Fosc) is 7.648 GHz, and the PLL output clock frequency (Fcy) is what we want to find.
Using the following formula for the PLL division factor:
N = Fosc / Fcy
We can rearrange the equation to solve for Fcy:
Fcy = Fosc / N
Now, we need to determine the value of N.
The primary oscillator frequency (Fosc) is provided as 7.648 GHz. However, this frequency is too high for the PLL to handle directly. The PLL can handle frequencies up to 80 MHz.
So, we need to find the maximum possible division factor that will still result in a frequency within the acceptable range.
Let's assume the maximum division factor is M.
M = Fosc / 80 MHz
M = 7.648 GHz / 80 MHz
M = 95.6
Therefore, the maximum division factor (M) is 95.6.
Now, we need to find the highest possible value for the division factor N.
To achieve this, we use the equation:
N = Ceiling(M / 2)
where Ceiling(.) is the ceiling function, which rounds the result up to the nearest integer.
N = Ceiling(95.6 / 2)
N = Ceiling(47.8)
N = 48
So, the division factor for the PLL (N) is 48.
Now, we can calculate Fcy.
Fcy = Fosc / N
Fcy = 7.648 GHz / 48
Fcy = 159.33 MHz
Therefore, the internal instruction cycle frequency (Fcy) is 159.33 MHz.
To calculate Tcy, we use the equation:
Tcy = 1 / Fcy
Tcy = 1 / 159.33 MHz
Tcy ≈ 6.279 ns
Therefore, the internal instruction cycle time (Tcy) is approximately 6.279 nanoseconds.
Question 2.
The primary oscillator in Explorer 16 is used as the clock source and its frequency is 7.648 GHz. The PLL is used. In that case, what is Fcy (Internal instruction cycle frequency)? Also, what is Tcy? You must show your calculation. Failing to do so will result zero mark for this question.
1 answer