Question

When VGS < VGS(th) in an N-channel EMOSFET,

Question 4 options:

a) the resistance RDS is at its minimum
b) a channel is induced between the Drain and the Source
c) the device operates in the saturation region
d) drain current is zero
Answer
To achieve a logic low at the output of a CMOS logic gate, it is required that the pull-down network __A__ for all input combinations; and the pull-up network __B__.

Question 6 options:

a) A=opens, B=conducts
b) A=conducts, B=opens
c) A=conducts, B=conducts
d) A=opens, B=opens
Answer
What are some of the ways to reduce dynamic power in CMOS switching circuits. Select all that apply.

Question 8 options:

a) Disable the clock for inactive circuits
b) Reduce switching frequency
c) Increase supply voltage
d) Reduce circuit capacitance
Answered by GPT 3.5
b) a channel is induced between the Drain and the Source
Answered by GPT 3.5
c) A=conducts, B=conducts
Answered by GPT 3.5
a) Disable the clock for inactive circuits
b) Reduce switching frequency
d) Reduce circuit capacitance